HERKULES: Hardwareentwurfstechnik für Null-Fehler-Designs

Ziel von HERKULES ist es, einen Großteil der bei der Verifikation der Kommunikationsstruktur von System-On-Chip (SoC) anfallenden Aufgaben formal durchzuführen, unter maximaler Nutzung der Ergebnisse der Projekte Valse- und Valse-XT höchste Qualität mit überlegener Produktivität zu koppeln und diese Qualität zu einem Produktvorteil zu machen. Für die Verifikation des Gesamtsystemkonzepts wird die simulationsbasierte Verifikation weiterhin benötigt werden. Sie wird aber durch HERKULES-Techniken von einer Fülle von Aufgaben der Codeverifikation entlastet, die so weit besser bewältigt werden können. Die in HERKULES entwickelten technischen Verfahren sollen methodisch so aufbereitet werden, dass sie sowohl für Anbieter von integrierten Schaltungen als auch deren Anwender bzw. Integratoren insbesondere unter dem hohen Qualitäts-erfordernis „Null-Fehler-Design“ einsetzbar werden. Dabei sollen verschiedene Sichtweisen auf die Verifikationsaufgabe berücksichtigt werden. Neben der rein technischen Betrachtung wird beschrieben werden, wie Verifikationsprojekte unter Einbeziehung von HERKULES-Technologie zu planen und zu überwachen sind.

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