LEONIDAS+: Leitbahnorientiertes Design

Das Projekt LEONIDAS+ baut auf den Arbeiten des Projekts LEONIDAS auf. Ziel von LEONIDAS+ ist die Durchführung von Forschungsarbeiten, die neue Lösungen für die Extraktion, die Analyse und Modellierung der Leitbahneigenschaften für SoCs zu finden. Die Vorhersagbarkeit der physikalischen Eigenschaften eines SoC-Entwurfs wird damit bereits in einem sehr frühen Stadium mit hoher Genauigkeit gewährleistet. Bisher separate Entwurfsschritte sollen mit neuartigen Algorithmen simultan ablaufen, so dass ein fehlerfreier Erstentwurf möglich wird. Konkret sollen folgende Anforderungen erfüllt werden:

• Kompatible Leitbahn-Constraints
• Hochgenaue Referenzsimulation zur Kalibrierung von Crosstalk-Problemen
• Behandlung von Prozessschwankungen auf Layoutebene
• Kopplung von Substrat- und Leitbahnmodellierung
• Timing-getriebener 3D-Platzierer für ICV
• Simultane Synthese und Platzierung von Leitbahnsystemen
• Automatisierte Berücksichtigung von Antiskew-Elementen bei der DfT-Prüfketten-Sortierung

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Projektkoordination: Infineon Technologies AG Dipl.-Math. Irmtraud Rugen-Herzig fon: +49 89 234-21046 irmtraud [dot] rugen-herziginfineon [dot] com Projektmanagement: Leibniz Universität Hannover Dr.-Ing. Markus Olbrich fon: +49 511 762-19661 markus [dot] olbrichims [dot] uni-hannover [dot] de Projektpartner: Atmel Germany GmbH Cadence Design Systems GmbH Infineon Technologies AG Leibniz Universität Hannover Philips Semiconductors Robert Bosch GmbH S3 Solutions GmbH Forschungspartner: Redemund und Thiede Datentechnik GmbH Technische Universität Darmstadt Technische Universität Dresden Universität Siegen Universität Ulm Förderkennzeichen: BMBF F&E 01M3074 Laufzeit: 01.03.2005 - 28.02.2007 Webseite: http://leonidas-plus.ims.uni-hannover.de

Projekt-Informationen Schlussbericht NL 03 2007 (PSB) NL 02 2007 (PN) NL 04 2006 (PN) NL 02 2006 (PN) NL 02 2006 (PB) NL 01 2006 (PN)

Verwendete Abkürzungen