Sigma65: Technologiebasierte Modellierung und Analyseverfahren unter Berücksichtigung von Streuungen im 65nm-Knoten

Im Vordergrund der geplanten Forschungen stehen die in den nächsten Jahren zur Einführung und vollen Entfaltung kommenden Technologieknoten (u. a. der 65nm-Technologieknoten). Aufgrund der abnehmenden Strukturgröße entstehen neue Beziehungen zwischen den Bauelementen auf dem Chip und ihrer Umgebung. Die Fertigungstoleranzen innerhalb eines Chips und von Chip zu Chip spielen im Sub-100nm-Bereich eine erhebliche Rolle und müssen wie schon erläutert bereits im Entwurfsprozess konsequent berücksichtigt werden. Im Projekt werden die eng mit der Technologie verbundenen Entwurfsebenen betrachtet. Das Projekt will Verfahren und Methoden erarbeiten, die ausgehend von den unteren (Transistor-) Entwurfsebenen abstrahierte Modelle mit statistischen Verteilungen der Parameter der höheren Entwurfsebenen (Gatter- und Blockniveau) generieren. Die neuen Modelle sollen technologienah die Effekte und Verhaltensweisen aufgrund von Schwankungen der Bauelementeigenschaften beschreiben und die Fertigungstoleranzen mit ihren Auswirkungen so genau wie nötig darstellen.

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Projektkoordination:

Fraunhofer Institut für Integrierte Schaltungen (IIS)
Dr.-Ing. Manfred W. Dietrich
fon: +49 351 4640-715
manfred [dot] dietricheas [dot] iis [dot] fraunhofer [dot] de